In view of the rapid ongoing development of computer technology, there is a need for a memory medium which makes it possible to store an ever greater quantity of information on ever smaller arrangements. In the field of non-volatile memories, which, once they have been programmed with the information item to be stored, retain this information item permanently without ever losing it, it is customary for data quantities of one bit or more to be stored in each transistor of a large arrangement of transistors. By way of example, Widmann, D, Mader, H, Friedrich, H (1996) “Technologie hochintegrierter Schaltungen” [Large-scale integrated circuit technology], Chapter 8.4, Springer Verlag, Berlin, ISBN 3-540-59357-8, provides a summary of non-volatile memories.
As miniaturization continues, conventional silicon microelectronics will reach its limits. In particular, the development of ever smaller and more densely arranged transistors, which has by now reached several hundred millions of transistors per chip, will come up against basic physical problems in the next ten years. When feature sizes drop below 80 nm, the components are disruptively affected by quantum effects, and these effects become dominant at sizes of below approximately 30 nm. Also, the increasing integration density of the components on a chip leads to a dramatic rise in the waste heat which is generated. Therefore, increasing the storage density of transistor arrangements by means of ongoing miniaturization of the structure dimensions is a concept which imposes high technological demands on the basic fabrication methods.
In the case of what is known as embedded technology, transistors with different requirements are integrated in a single integrated circuit, i.e. in a chip. For example, it may be necessary to integrate transistors of different configurations in a memory region of the chip (for example in a flash memory arrangement or an EEPROM) and in a logic region of the integrated circuit. In a scenario of this nature, different demands are imposed on the structural and physical parameters of the integrated transistors.
To form a transistor in a logic region, which logic region is to be sufficiently fast, a logic transistor of this type needs to be separated from its surroundings by a side wall oxide layer which is as thin as possible. A thin side wall oxide layer is necessary in a logic transistor in order to ensure a low connection resistance: a layer arrangement which serves as a logic transistor on a substrate can be coupled to the surroundings by doping atoms being injected into the boundary regions on both sides between the laterally delimited layer arrangement and the substrate (“lightly doped drain”). If in the case of a logic transistor, the side wall oxide layer is too thick, the region of overlap between the doped region in the silicon substrate and the gate oxide region of the transistor is small, and consequently the logic transistor has a high impedance. In other words, the further the lightly doped drain regions are formed outside the end sections of the logic transistor on both sides, the higher the impedance of the logic transistor becomes. To ensure that the logic transistor is sufficiently fast, the side wall oxide layer of the logic transistor should therefore be sufficiently thin (e.g. approx. 5 nm to 7 nm for the 130 nm technology generation). On the other hand, it is important for a side wall oxide layer to be present in a logic region, in order to form a well-defined surface at the side wall of the gate electrode made from polysilicon (polycrystalline silicon), in order to saturate surface charges as occur, for example, during the method of fabricating the logic transistor and to anneal plasma etching damage as may occur, for example, during the CVD (chemical vapor deposition) process which is frequently used in the fabrication of transistors.
On the other hand, it is aimed for the side wall oxide layer of a memory transistor in a flash memory or an EEPROM memory to be a sufficiently thick side wall oxide layer. A sufficiently thick side wall oxide layer ensures in a charge-storage layer that the information which is stored in the memory transistor and is coded in the amount of electric charge contained in the charge-storage layer is reliably retained. This leads to a sufficiently long hold time for the stored information, which is essential for the functionality of a memory transistor. Furthermore, a thick side wall oxide layer in a memory transistor leads to the avoidance of ion damage at the tunnel oxide edge, which adversely affects the functionality of a memory transistor, and to the avoidance of undesirable charging of the floating gate by subsequent implantations of ions for forming doped regions in surface regions of a substrate. Furthermore, a sufficiently thick side wall oxide layer keeps boundary charges caused by a silicon nitride spacer which is often formed during fabrication of the memory transistor away from the floating gate or from the gate oxide layer, thus ensuring perfect functionality of the memory transistor. The thickness of the side wall oxide in a memory transistor should be at least 10 nm.
The contradictory demands imposed on the thicknesses of the side wall oxide layers in a logic transistor and in a memory transistor on a chip which has both a logic region with rapid integrated logic for driving the memory region and a memory region with a multiplicity of memory transistors are often only taken into account in the prior art to the extent that a uniform thickness is selected for the side wall oxide layers of the logic transistors and the memory transistors. This uniform thickness is selected to be sufficiently small to obtain a logic transistor with a side wall thickness which is reasonably acceptable in the logic region and is also selected to be sufficiently great to obtain a memory transistor with a reasonably acceptable side wall thickness in the memory region. However, this compromise solution adversely affects the functionality of both types of transistors for the reasons listed above.
A compromise solution of this type is increasingly unsuitable for technologies which deal with transistors with a gate region length of 130 nm and below, if perfect functionality of the integrated circuits which these technologies produce is to be ensured. For a transistor with a gate region length of 130 nm and below, a side wall oxide thickness of significantly less than 10 nm is required for a perfectly functioning, sufficiently fast logic transistor, but this thickness is much too low for a memory transistor in a flash memory or an EEPROM.
The prior art has disclosed a method which makes it possible to fabricate an integrated circuit having a logic region with a logic transistor and a memory region with a memory transistor integrated on a common chip and in which the side wall oxide of the logic transistor and of the memory transistor can be formed in different thicknesses.
A method of this type, which involves the formation of logic transistors with a side wall oxide which is thinner than the side wall oxide of memory transistors formed on the same integrated circuit is described below with reference to FIGS. 1A-1I.
In the abovementioned figures, a left-hand region of the layer structures shown in each case represents a logic region of an integrated circuit (or more specifically a logic transistor of the logic region), and the region shown on the right-hand side represents a memory region (or more specifically a memory transistor of the memory region) of the integrated circuit. This is visually indicated in FIGS. 1A-1I by the fact that a dashed vertical line is included in the drawing, separating the logic region formed to the left of the dashed line from the memory region shown to the right of the dashed line.
To arrive at the layer structure 100 shown in FIG. 1A, a first silicon dioxide layer 102, a first polysilicon layer 103 and an ONO layer sequence 104 are deposited on a silicon substrate 101. An ONO layer sequence is a three-layer sequence comprising in each case one layer of silicon dioxide, silicon nitride and silicon dioxide. The first of the silicon dioxide layers of the ONO layer sequence 104 is deposited on the first polysilicon layer 103, the silicon nitride layer of the ONO layer sequence 104 is deposited on the first silicon dioxide layer of the ONO layer sequence 104, and the second silicon dioxide layer of the ONO layer sequence 104 is deposited on the silicon nitride layer of the ONO layer sequence 104.
The layer structure 105 shown in FIG. 1B is obtained by removing the first silicon dioxide layer 102, the first polysilicon layer 103 and the ONO layer sequence 104 from the entire logic region using a lithography process and an etching process.
To convert the layer structure 105 shown in FIG. 1B into the layer structure 106 shown in FIG. 1C, a second silicon dioxide layer 107, a second polysilicon layer 108 and a suitable hard mask 109 are deposited over the entire surface of the layer structure 105.
The layer structure 110 shown in FIG. 1D is obtained by the layer structure being patterned in the memory region (i.e. in the region to the right of the dashed line in FIG. 1C, FIG. 1D), whereas the logic region (region to the left of the dashed line in FIG. 1C, FIG. 1D) is covered. Since the structures formed in the memory region must lie within a small structural tolerance range, this patterning step is of crucial importance. This means that even slight inaccuracies in this method step will have a considerable influence on the functionality of the integrated circuit fabricated in this way. Therefore, this method step requires accurate setting of the process conditions, making this method step complex and expensive. As shown in FIG. 1D, only the top five layers are patterned in the memory region, whereas the first silicon dioxide layer 102 is retained in the memory region as well. This can be achieved by using a suitable etching process which is set up in such a manner that the etching process stops before the first silicon dioxide layer 102.
To achieve the layer structure 111 shown in FIG. 1E, the laterally delimited layer sequence which remains in the memory region after the patterning is covered with a first side wall oxide layer 112. This side wall oxide initially also grows on surface regions other than the laterally delimited layer sequence, including over the layers 102 and 109, and can be etched back, resulting in the layer sequence 111 shown in FIG. 1E. This leads to only a slight raising of the hard mask layer 109 (not shown) in the entire logic region during this method step. In other words, the side wall of the laterally delimited layer sequence in the memory region is covered with the first side wall oxide layer 112, whereas the logic region remains virtually unchanged.
The layer structure 113 shown in FIG. 1F is obtained by keeping the logic region covered while doping atoms are introduced into those surface regions of the silicon substrate 101 which are not covered by the laterally delimited layer sequence, using an ion implantation method, with the result that the LDD (lightly doped drain) regions 114a, 114b are formed.
To achieve the layer structure 115 shown in FIG. 1G, the memory region is then completely covered and the logic region is patterned using a lithography process and an etching process. To pattern the logic region into a laterally delimited layer sequence, a further patterning step of crucial importance is required. This means that even slight fluctuations in the procedure will immediately have an adverse effect on the functionality of the logic regions formed in this way. As with the first critical patterning step described above, this method step too requires a complex and expensive procedure which needs to be highly accurate. As shown in FIG. 1G, only the top two layers, namely the second polysilicon layer 108 and the hard mask 109, are patterned, whereas the second silicon dioxide layer 107 is not removed from the surface of the layer structure arranged in the logic region as a result of a suitable etching process being used. Consequently, the laterally delimited layer sequence which is shown in FIG. 1G and comprises the second polysilicon layer 108 and the hard mask 109 remains in place on the logic region.
The layer structure 116 shown in FIG. 1H is obtained by in each case applying a second side wall oxide layer 117 to the laterally delimited layer sequences in both the logic region and in the memory region of the flash memory or EEPROM. This is achieved by thermal oxidation of the side walls. The second side wall oxide layer 117 has a lower thickness than the first side wall oxide layer 112. As shown in FIG. 1H, the laterally delimited layer sequence in the logic region therefore includes a side wall oxide which corresponds to the thickness of the second side wall oxide layer 117, whereas the laterally delimited layer sequence in the memory region includes a side wall oxide layer whose thickness is composed of the thickness of the first side wall oxide layer 112 and the thickness of the second side wall oxide layer 117.
To achieve the layer structure 118 shown in FIG. 1I, implantation steps are carried out in both the logic region and the memory region, with the result that the first doped region 119a and the second doped region 119b are obtained in the logic region. In this way, the first HDD region 120a and the second HDD region 120b are produced in the memory region at the end sections of the laterally delimited layer sequences on both sides. HDD means highly doped drain, expressing the fact that the concentration of doping atoms in the HDD regions 120a, 120b is greater than in the LDD regions 114a, 114b. The laterally delimited layer sequence formed in the logic region forms a transistor with a side wall oxide having the thickness of the second side wall oxide layer 117. The first doped region 119a represents the first source/drain region, whereas the second doped region 119b forms the second source/drain region. The second silicon oxide layer 107 in the logic region forms the gate oxide layer, and the second polysilicon layer 108 forms the gate electrode in the logic region. The second side wall oxide layer 117 is used to laterally shield the transistor, and the hard mask 109 is likewise used as a protective layer.
The laterally delimited layer sequence formed in the memory region can be used as a memory transistor. The first LDD region 114a and the first HDD region 120a form the first source/drain region, the second LDD region 114b and the second HDD region 120b form the second source/drain region. The first silicon dioxide layer 102 constitutes the gate oxide region. The first polysilicon layer 103 can fulfill the functionality of a floating gate into which charge carriers can be permanently injected, for example by means of Fowler-Nordheim tunneling or by means of hot electrons. The ONO layer sequence 104 and the second silicon dioxide layer 107 effect electrical decoupling of the floating gate from the second polysilicon layer 108, which can perform the functionality of a gate electrode. The hard mask 109 represents a protective layer, and a sufficiently thick side wall oxide layer of the memory transistor is produced by means of the first side wall oxide layer 112 and the second side wall oxide layer 117.
However, the above-described method for forming logic transistors and memory transistors with different side wall oxide thicknesses has a number of drawbacks. As described above, two critical lithography steps are required during the method, and even slight deviations in these steps lead to wide-ranging negative consequences for the functionality of the arrangement. The execution of these two critical lithography steps makes fabrication of the layer structure 118 complex and expensive.
A further drawback of the fabrication method described is based on the fact that the gate patterning of the logic transistors, on the one hand, and of the memory transistors, on the other hand, are carried out in two separate method steps. The patterning of the memory transistors takes place in the method step in which the layer structure 110 shown in FIG. 1D is formed from the layer structure 106 shown in FIG. 1C. By contrast, the patterning of the logic transistors takes place in the method step in which the layer structure 115 shown in FIG. 1G is formed from the layer structure 113 shown in FIG. 1F. In practice, it is not possible to set absolutely identical conditions for these two method steps. However, it is important to provide structures with a homogenous surface coverage density in the logic region, on the one hand, and in the memory region, on the other hand. The surface coverage density is defined as the ratio of the sum of the areas which are covered in the logic or memory region divided by the total surface area of the logic region or of the memory region. The surface coverage density should ideally be as homogenous as possible over the entire chip, in order to be able to ensure minimal tolerances during fabrication of the gate electrodes.
If the surface coverage densities achieved by the two above-described method steps for patterning of the logic transistors, on the one hand, and the memory transistors, on the other hand, deviate from one another, the result will be a variation in the geometry of the gate electrode. Adverse effects which result from an uneven surface coverage density are referred to as etch loading effects. These have an adverse effect on the functionality of the integrated circuit formed. Therefore, the quality of the transistors which are fabricated using the method described is often poor.
U.S. Pat. No. 5,291,052 discloses a CMOS semiconductor device with a p-MOS transistor and with an n-MOS transistor on a wafer.
U.S. Pat. No. 6,160,317 discloses a method for fabricating a semiconductor device which allows etching of a field oxide while minimizing damage to the silicon.
German Patent No. DE 196 54 738 A1 discloses a method for fabricating a semiconductor memory device with n-MOS and p-MOS transistors with different properties.
Great Britain Patent No. GB 2,359,662 discloses a semiconductor device with a DRAM cell.
Accordingly, there is an need to overcome the problem of providing laterally delimited layer sequences with different side wall thicknesses on a common substrate with a reduced level of outlay and in an improved quality.